1. Field of the Invention
The present invention relates to methods for forming semiconductor devices including deposited films, particularly, silicon-based deposited films, and methods for forming photovoltaic devices, such as solar cells, including silicon-based deposited films.
2. Description of the Related Art
High-frequency plasma-enhanced chemical vapor deposition (CVD) is one superior method for mass production of silicon-based deposited films because this method facilitates formation of large films at low temperature with high process throughput. Examples of applications of such silicon-based deposited films for products include solar cells. In comparison with existing energy generation systems using fossil fuels, solar cells including silicon-based deposited films have the advantage of using an infinite energy source and a clean power generation process. However, a further cost reduction is required to promote widespread use. Accordingly, the development of techniques for increasing the deposition rate in high-frequency plasma-enhanced CVD and achieving a further improvement in characteristics is an important technological issue.
A method for forming a crystalline silicon-based deposited film layer is disclosed in, for example, Japanese Patent Laid-Open No. 11-330520. According to this publication, a deposited film is formed on a substrate in a reaction chamber containing a silane-family gas and hydrogen gas at a pressure of 5 Torr or more, and having an interelectrode distance of 1 cm or less. The publication discloses that a silicon-based film layer can be deposited at high speed under such conditions and that a photoelectric conversion device including the deposited film has high conversion efficiency.
U.S. Pat. No. 6,326,304 discloses a technique for forming an amorphous silicon-based deposited film under the following conditions. That is, the deposited film is formed at a silane-family gas partial pressure of 1.2 to 5.0 Torr and an interelectrode distance of 8 to 15 mm using a hydrogen diluent gas in an amount of not more than four times that of the silane-family gas.
U.S. Pat. No. 6,483,021 discloses a stacked photovoltaic device including at least two p-i-n junction devices stacked on top of each other, one including an i-type microcrystalline semiconductor layer and another including an i-type amorphous semiconductor layer. In this stacked photovoltaic device, the p-i-n junction device including the i-type microcrystalline semiconductor layer determines current to suppress optical degradation of the photovoltaic device and improve its characteristics.
Other plasma-enhanced CVD techniques have been proposed in which the conditions where an i-type deposited film is formed are appropriately controlled to improve the characteristics of semiconductor devices including photoelectric conversion elements.
Japanese Patent Laid-Open No. 63-220578, for example, discloses a photovoltaic device including a photoelectric conversion element including first and second deposited films that are substantially intrinsic. The first deposited film is thinner than the second deposited film. The first deposited film is formed at a higher pressure than the second deposited film to improve the open-circuit voltage characteristics and short-circuit current characteristics of the photovoltaic device.
European Patent No. 0151754 (B1) discloses a technique for controlling the conditions where an amorphous intrinsic semiconductor layer is formed when an amorphous silicon semiconductor device is formed. Specifically, the main part of the amorphous intrinsic semiconductor layer is deposited by microwave plasma discharge before the rest of the semiconductor layer, thinner than the main part, is deposited by RF plasma discharge. This method can improve both the rate at which the deposited film is formed and the characteristics of the semiconductor device.
Japanese Patent Publication No. 7-99776 discloses a method in which a hydrogen-diluted silane gas is used to deposit an i-type layer in contact with a p-type layer and a 100% silane gas is used to deposit a bulk i-type layer. The i-type layer in contact with the p-type layer and the bulk i-type layer can be deposited at different deposition rates to suppress a deterioration in interface properties and to improve characteristics and mass productivity.
Japanese Patent Laid-Open Nos. 6-85291, 2000-183377, and 2000-243992 disclose techniques for changing the deposition rate when an i-type non-single-crystal silicon-based semiconductor layer or an i-type crystalline silicon-based photoelectric conversion layer is formed. A photoelectric conversion layer thus formed provides a high-quality semiconductor device or photoelectric conversion device that can suppress optical degradation and has high efficiency and stability.
Japanese Patent Laid-Open No. 61-119030 and Japanese Patent Publication No. 61-47225 disclose techniques for applying a positive DC bias voltage to a substrate electrode or applying a DC bias to either discharge electrode when an amorphous semiconductor layer is formed. The DC bias can be controlled to increase the deposition rate.
Japanese Patent Laid-Open No. 59-97514 discloses a technique for forming an amorphous silicon film on a substrate while applying a DC voltage to a conductive portion of the substrate to control the optical energy gap.
Japanese Patent Laid-Open No. 57-159070 discloses a technique for forming an i-type amorphous silicon film on the light-incidence side at a lower substrate temperature than on the light-transmission side. Such temperature control allows the hydrogen content and forbidden band width of the amorphous silicon film to be controlled, thereby improving photoelectric conversion efficiency.
The characteristics of silicon-based deposited films formed by plasma-enhanced CVD have gradually been improved by techniques as disclosed in the patent documents described above. For example, a silicon deposited film containing crystals with relatively superior characteristics can be formed at a high deposition rate, namely, 1 nm/s or more, by plasma-enhanced CVD at relatively high pressure (for example, 600 Pa or more) and short interelectrode distance (for example, 10 mm or less). Semiconductor devices produced by the above techniques, including photovoltaic devices such as solar cells, have superior characteristics, for example, increased conversion efficiency and suppressed degradation rate.
However, some problems must be solved to further improve the characteristics of photovoltaic devices including silicon deposited films containing crystals, and to reduce their costs.
Reducing structural defects in a deposited film being formed is important for forming a silicon film containing crystals (hereinafter referred to as a microcrystalline silicon film) with superior characteristics. It is also important to form a deposited film without causing cation damage to the surface of the deposited film being formed.
Techniques of controlling some parameters in a process of forming a deposited film by plasma-enhanced CVD are known, as disclosed in the above patent documents. Specifically, a deposited film with adequate quality can be formed by appropriately controlling, for example, interelectrode distance, pressure, source gas flow rate, diluent gas flow rate, ratio in gas flow rate, frequency of high-frequency power, deposition rate, and bias voltage. However, a further improvement has been desired to suppress formation of structural defects in a microcrystalline silicon film being formed, and to suppress cation damage.
A first problem is (1) induction of sparks that destabilize plasma and (2) increased growth of fine particles of byproducts such as polysilane in the plasma, depending on the conditions where the deposited film is formed. The sparks adversely affect the characteristics of the deposited film because they increase, for example, structural defects in the deposited film.
The term “sparks” used in the present invention refers to a sudden transition from glow discharge to arc discharge (one type of abnormal discharge).
If a spark occurs on the surface of the deposited film, the spark itself damages the surface of the deposited film, thus forming a structural defect. Even if the spark occurs at a site other than the surface of the deposited film, the discharge undergoes momentary interruption at the instant of occurrence of the spark, thus forming a discontinuous interface in the deposited film. Such an interface can adversely affect, for example, the electrical or optical characteristics of the deposited film. In addition, while the spark is occurring, a polymerization reaction of active species is predominant in the deposition chamber because the high-frequency energy does not contribute to decomposition of the source gas. This promotes growth of fine particles of, for example, polysilane.
The findings of the inventors show that such sparks do not occur uniformly, but occur at different sites for different durations. For example, the sparks tend to occur at edges, such as those of a substrate and a high-frequency electrode, and in the peripheries thereof. In the step of forming the deposited film, additionally, the sparks can be induced by changes in the relative positions of the substrate and the high-frequency electrode due to, for example, thermal stress or transfer of the substrate. For example, many sparks tend to occur at a site where the distance between the high-frequency electrode and the substrate (interelectrode distance) is slightly or significantly changed instantaneously.
The sparks also vary in duration (spark duration) according to detailed data. Specifically, the sparks include extremely small sparks with durations of several microseconds or less, sparks with durations of several microseconds to several tens of microseconds, sparks with durations of several tens of microseconds to several tens of milliseconds, sparks with durations of several tens of milliseconds to several hundreds of milliseconds, and sparks with durations of several hundreds of milliseconds or more. Sparks with longer durations have a larger adverse effect on the deposited film.
It has been known that sparks occur in the step of forming a deposited film by plasma-enhanced CVD. However, extremely small sparks (with spark durations of several microseconds to several tens of milliseconds) have not been understood in detail because they are difficult to visually recognize and the discharge remains apparently stable.
A spark killer (a device that detects a change in bias current and reduces or interrupts the voltage being applied upon detection of a predetermined value of current) is known for use as a spark-suppressing device, but sparks are difficult to completely avoid. For example, if the sensitivity of the spark killer is increased, the bias voltage is frequently interrupted due to noise other than sparks. This makes it difficult to perform stable discharge. Accordingly, while spark killers are intended to suppress the frequency of occurrence or magnitude of sparks, they cannot always sufficiently suppress the occurrence of small sparks.
As described above, optimizing the conditions where a deposited film is formed is not easy because the occurrence of sparks and fine particles of, for example, polysilane can be induced.
A second problem is the difficulty of forming a microcrystalline silicon film with an appropriate grain size and few structural defects to increase conversion efficiency.
According to the findings of the inventors, a deposited film containing microcrystalline silicon cannot provide a sufficient open-circuit voltage and has low short-circuit current when used for solar cells if the film has a small crystal grain size or includes numerous defects at its crystal grain boundaries. The deposited film also has the problem of a decrease in film quality over time which leads to, for example, decreased electrical characteristics.
In addition, the content of microcrystals in the deposited film can be decreased, and the amorphous content can be increased correspondingly, depending on the conditions where the deposited film is formed. If such a deposited film is exposed to extended light irradiation, weak bonds included in the molecular network are cleaved and the number of dangling bonds is increased accordingly, depending on the thickness of the deposited film. This adversely affects the characteristics of the deposited film. If such a deposited film is used as an i-type layer of a p-i-n junction photoelectric conversion element in a solar cell, for example, its characteristics can be significantly decreased due to optical degradation, depending on the layer structure of the solar cell.
The characteristics of the deposited film thus depend on the conditions where the film is formed. The findings of the inventors show that it is effective to suppress cation damage to the deposited film.
If the conditions where the deposited film is formed are controlled only in view of cation damage, however, the rate at which the deposited film is formed may be decreased, and the characteristics of the deposited film may be degraded due to factors other than cation damage (for example, a change in the state of plasma). This makes it difficult to form a deposited film containing microcrystals with characteristics that are optimum for photovoltaic devices such as solar cells.
The patent documents described above disclose no technique effective against the first and second problems.
Japanese Patent Laid-Open No. 11-330520 and U.S. Pat. Nos. 6,326,304 and 6,483,021 contain no disclosure as to suppression of cation damage in separate steps for forming an i-type silicon-based deposited film layer or as to suppression of sparks.
Japanese Patent Laid-Open No. 63-220578 discloses the technique for controlling the pressure at which an i-type layer is formed. Because plasma potential generally decreases with increasing pressure, the first substantially intrinsic deposited film, which is thinner than the second substantially intrinsic deposited film, will suffer a smaller cation damage than the second deposited film. This publication, however, contains no sufficient disclosure as to control of cation damage with bias voltage, as to formation of an i-type microcrystalline silicon layer, or as to suppression of sparks.
European Patent No. 0151754 (B1) discloses a technique for controlling the frequency of high-frequency power when an intrinsic amorphous semiconductor layer is formed. This publication, however, contains no sufficient disclosure as to control of cation damage with bias voltage, as to suppression of sparks, or as to microcrystalline silicon.
Japanese Patent Publication No. 7-99776 contains no sufficient disclosure as to control of cation damage with bias voltage, as to suppression of sparks, or as to microcrystalline silicon.
Japanese Patent Laid-Open Nos. 6-85291, 2000-183377, and 2000-243992 contain no disclosure as to control of cation damage with bias voltage or as to suppression of sparks.
Japanese Patent Laid-Open No. 61-119030 and Japanese Patent Publication No. 61-47225 disclose techniques for applying a positive DC bias voltage to a substrate electrode, or applying a DC bias to either discharge electrode, and controlling the DV bias when an amorphous semiconductor layer is formed. These publications, however, contain no disclosure as to control of cation damage to a microcrystalline silicon film with bias voltage or as to suppression of sparks. The application of the DC bias does not directly result in reduced cation damage. In addition, the plasma itself also varies with the polarity of the bias voltage and the type of electrode to which the voltage is applied, and the effect of the bias varies accordingly. For example, the electrical characteristics of an amorphous silicon film can be improved by forcing cations to collide with the deposited film (ion bombardment), unlike a microcrystalline silicon film. This is probably because the ion bombardment locally anneals the deposited film to promote its structural relaxation. On this point, microcrystalline silicon films in the present invention differ significantly from amorphous silicon films in the effect of application of bias voltage.
Japanese Patent Laid-Open Nos. 59-97514 and 57-159070 contain no disclosure as to control of cation damage to a microcrystalline silicon film with bias voltage or as to suppression of sparks.
Furthermore, none of the above patent documents discloses a technique for suppressing sparks (particularly, extremely small sparks) in a step of forming a deposited film.